rte_eth_ctrl.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2015 Intel Corporation
 */

#ifndef _RTE_ETH_CTRL_H_
#define _RTE_ETH_CTRL_H_

#include <stdint.h>
#include <rte_common.h>
#include "rte_ether.h"
#include "rte_flow.h"

#ifdef __cplusplus
extern "C" {
#endif

enum rte_filter_type {
    RTE_ETH_FILTER_NONE = 0,
    RTE_ETH_FILTER_MACVLAN,
    RTE_ETH_FILTER_ETHERTYPE,
    RTE_ETH_FILTER_FLEXIBLE,
    RTE_ETH_FILTER_SYN,
    RTE_ETH_FILTER_NTUPLE,
    RTE_ETH_FILTER_TUNNEL,
    RTE_ETH_FILTER_FDIR,
    RTE_ETH_FILTER_HASH,
    RTE_ETH_FILTER_L2_TUNNEL,
    RTE_ETH_FILTER_GENERIC,
    RTE_ETH_FILTER_MAX
};

enum rte_filter_op {
    RTE_ETH_FILTER_NOP = 0,
    RTE_ETH_FILTER_ADD,      
    RTE_ETH_FILTER_UPDATE,   
    RTE_ETH_FILTER_DELETE,   
    RTE_ETH_FILTER_FLUSH,    
    RTE_ETH_FILTER_GET,      
    RTE_ETH_FILTER_SET,      
    RTE_ETH_FILTER_INFO,     
    RTE_ETH_FILTER_STATS,    
    RTE_ETH_FILTER_OP_MAX
};

enum rte_mac_filter_type {
    RTE_MAC_PERFECT_MATCH = 1, 
    RTE_MACVLAN_PERFECT_MATCH, 
    RTE_MAC_HASH_MATCH, 
    RTE_MACVLAN_HASH_MATCH,
};

struct rte_eth_mac_filter {
    uint8_t is_vf; 
    uint16_t dst_id; 
    enum rte_mac_filter_type filter_type; 
    struct rte_ether_addr mac_addr;
};

#define RTE_ETHTYPE_FLAGS_MAC    0x0001 
#define RTE_ETHTYPE_FLAGS_DROP   0x0002 
struct rte_eth_ethertype_filter {
    struct rte_ether_addr mac_addr;   
    uint16_t ether_type;          
    uint16_t flags;               
    uint16_t queue;               
};

#define RTE_FLEX_FILTER_MAXLEN  128 
#define RTE_FLEX_FILTER_MASK_SIZE   \
    (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)

struct rte_eth_flex_filter {
    uint16_t len;
    uint8_t bytes[RTE_FLEX_FILTER_MAXLEN];  
    uint8_t mask[RTE_FLEX_FILTER_MASK_SIZE];    
    uint8_t priority;
    uint16_t queue;       
};

struct rte_eth_syn_filter {
    uint8_t hig_pri;     
    uint16_t queue;      
};

#define RTE_NTUPLE_FLAGS_DST_IP    0x0001 
#define RTE_NTUPLE_FLAGS_SRC_IP    0x0002 
#define RTE_NTUPLE_FLAGS_DST_PORT  0x0004 
#define RTE_NTUPLE_FLAGS_SRC_PORT  0x0008 
#define RTE_NTUPLE_FLAGS_PROTO     0x0010 
#define RTE_NTUPLE_FLAGS_TCP_FLAG  0x0020 
#define RTE_5TUPLE_FLAGS ( \
        RTE_NTUPLE_FLAGS_DST_IP | \
        RTE_NTUPLE_FLAGS_SRC_IP | \
        RTE_NTUPLE_FLAGS_DST_PORT | \
        RTE_NTUPLE_FLAGS_SRC_PORT | \
        RTE_NTUPLE_FLAGS_PROTO)

#define RTE_2TUPLE_FLAGS ( \
        RTE_NTUPLE_FLAGS_DST_PORT | \
        RTE_NTUPLE_FLAGS_PROTO)

#define TCP_URG_FLAG 0x20
#define TCP_ACK_FLAG 0x10
#define TCP_PSH_FLAG 0x08
#define TCP_RST_FLAG 0x04
#define TCP_SYN_FLAG 0x02
#define TCP_FIN_FLAG 0x01
#define TCP_FLAG_ALL 0x3F

struct rte_eth_ntuple_filter {
    uint16_t flags;          
    uint32_t dst_ip;         
    uint32_t dst_ip_mask;    
    uint32_t src_ip;         
    uint32_t src_ip_mask;    
    uint16_t dst_port;       
    uint16_t dst_port_mask;  
    uint16_t src_port;       
    uint16_t src_port_mask;  
    uint8_t proto;           
    uint8_t proto_mask;      
    uint8_t tcp_flags;
    uint16_t priority;       
    uint16_t queue;          
};

#define ETH_TUNNEL_FILTER_OMAC  0x01 
#define ETH_TUNNEL_FILTER_OIP   0x02 
#define ETH_TUNNEL_FILTER_TENID 0x04 
#define ETH_TUNNEL_FILTER_IMAC  0x08 
#define ETH_TUNNEL_FILTER_IVLAN 0x10 
#define ETH_TUNNEL_FILTER_IIP   0x20 
#define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
                    ETH_TUNNEL_FILTER_IVLAN)
#define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
                    ETH_TUNNEL_FILTER_IVLAN | \
                    ETH_TUNNEL_FILTER_TENID)
#define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
                    ETH_TUNNEL_FILTER_TENID)
#define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
                    ETH_TUNNEL_FILTER_TENID | \
                    ETH_TUNNEL_FILTER_IMAC)

enum rte_tunnel_iptype {
    RTE_TUNNEL_IPTYPE_IPV4 = 0, 
    RTE_TUNNEL_IPTYPE_IPV6,     
};

struct rte_eth_tunnel_filter_conf {
    struct rte_ether_addr outer_mac;    
    struct rte_ether_addr inner_mac;    
    uint16_t inner_vlan;            
    enum rte_tunnel_iptype ip_type; 
    union {
        uint32_t ipv4_addr;     
        uint32_t ipv6_addr[4];  
    } ip_addr;
    uint16_t filter_type;
    enum rte_eth_tunnel_type tunnel_type; 
    uint32_t tenant_id;     
    uint16_t queue_id;      
};

enum rte_eth_global_cfg_type {
    RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
    RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
    RTE_ETH_GLOBAL_CFG_TYPE_MAX,
};

struct rte_eth_global_cfg {
    enum rte_eth_global_cfg_type cfg_type; 
    union {
        uint8_t gre_key_len; 
        uint64_t reserved; 
    } cfg;
};

#define RTE_ETH_FDIR_MAX_FLEXLEN 16  
#define RTE_ETH_INSET_SIZE_MAX   128 
enum rte_eth_input_set_field {
    RTE_ETH_INPUT_SET_UNKNOWN = 0,

    /* L2 */
    RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
    RTE_ETH_INPUT_SET_L2_DST_MAC,
    RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
    RTE_ETH_INPUT_SET_L2_INNER_VLAN,
    RTE_ETH_INPUT_SET_L2_ETHERTYPE,

    /* L3 */
    RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
    RTE_ETH_INPUT_SET_L3_DST_IP4,
    RTE_ETH_INPUT_SET_L3_SRC_IP6,
    RTE_ETH_INPUT_SET_L3_DST_IP6,
    RTE_ETH_INPUT_SET_L3_IP4_TOS,
    RTE_ETH_INPUT_SET_L3_IP4_PROTO,
    RTE_ETH_INPUT_SET_L3_IP6_TC,
    RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
    RTE_ETH_INPUT_SET_L3_IP4_TTL,
    RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,

    /* L4 */
    RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
    RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
    RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
    RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
    RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
    RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
    RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,

    /* Tunnel */
    RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
    RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
    RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
    RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
    RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,

    /* Flexible Payload */
    RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
    RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
    RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
    RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
    RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
    RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
    RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
    RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,

    RTE_ETH_INPUT_SET_DEFAULT = 65533,
    RTE_ETH_INPUT_SET_NONE = 65534,
    RTE_ETH_INPUT_SET_MAX = 65535,
};

enum rte_filter_input_set_op {
    RTE_ETH_INPUT_SET_OP_UNKNOWN,
    RTE_ETH_INPUT_SET_SELECT, 
    RTE_ETH_INPUT_SET_ADD,    
    RTE_ETH_INPUT_SET_OP_MAX
};


struct rte_eth_input_set_conf {
    uint16_t flow_type;
    uint16_t inset_size;
    enum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX];
    enum rte_filter_input_set_op op;
};

struct rte_eth_l2_flow {
    uint16_t ether_type;          
};

struct rte_eth_ipv4_flow {
    uint32_t src_ip;      
    uint32_t dst_ip;      
    uint8_t  tos;         
    uint8_t  ttl;         
    uint8_t  proto;       
};

struct rte_eth_udpv4_flow {
    struct rte_eth_ipv4_flow ip; 
    uint16_t src_port;           
    uint16_t dst_port;           
};

struct rte_eth_tcpv4_flow {
    struct rte_eth_ipv4_flow ip; 
    uint16_t src_port;           
    uint16_t dst_port;           
};

struct rte_eth_sctpv4_flow {
    struct rte_eth_ipv4_flow ip; 
    uint16_t src_port;           
    uint16_t dst_port;           
    uint32_t verify_tag;         
};

struct rte_eth_ipv6_flow {
    uint32_t src_ip[4];      
    uint32_t dst_ip[4];      
    uint8_t  tc;             
    uint8_t  proto;          
    uint8_t  hop_limits;     
};

struct rte_eth_udpv6_flow {
    struct rte_eth_ipv6_flow ip; 
    uint16_t src_port;           
    uint16_t dst_port;           
};

struct rte_eth_tcpv6_flow {
    struct rte_eth_ipv6_flow ip; 
    uint16_t src_port;           
    uint16_t dst_port;           
};

struct rte_eth_sctpv6_flow {
    struct rte_eth_ipv6_flow ip; 
    uint16_t src_port;           
    uint16_t dst_port;           
    uint32_t verify_tag;         
};

struct rte_eth_mac_vlan_flow {
    struct rte_ether_addr mac_addr;  
};

enum rte_eth_fdir_tunnel_type {
    RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
    RTE_FDIR_TUNNEL_TYPE_NVGRE,
    RTE_FDIR_TUNNEL_TYPE_VXLAN,
};

struct rte_eth_tunnel_flow {
    enum rte_eth_fdir_tunnel_type tunnel_type; 
    uint32_t tunnel_id;
    struct rte_ether_addr mac_addr;            
};

union rte_eth_fdir_flow {
    struct rte_eth_l2_flow     l2_flow;
    struct rte_eth_udpv4_flow  udp4_flow;
    struct rte_eth_tcpv4_flow  tcp4_flow;
    struct rte_eth_sctpv4_flow sctp4_flow;
    struct rte_eth_ipv4_flow   ip4_flow;
    struct rte_eth_udpv6_flow  udp6_flow;
    struct rte_eth_tcpv6_flow  tcp6_flow;
    struct rte_eth_sctpv6_flow sctp6_flow;
    struct rte_eth_ipv6_flow   ipv6_flow;
    struct rte_eth_mac_vlan_flow mac_vlan_flow;
    struct rte_eth_tunnel_flow   tunnel_flow;
};

struct rte_eth_fdir_flow_ext {
    uint16_t vlan_tci;
    uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
    uint8_t is_vf;   
    uint16_t dst_id; 
};

struct rte_eth_fdir_input {
    uint16_t flow_type;
    union rte_eth_fdir_flow flow;
    struct rte_eth_fdir_flow_ext flow_ext;
};

enum rte_eth_fdir_behavior {
    RTE_ETH_FDIR_ACCEPT = 0,
    RTE_ETH_FDIR_REJECT,
    RTE_ETH_FDIR_PASSTHRU,
};

enum rte_eth_fdir_status {
    RTE_ETH_FDIR_NO_REPORT_STATUS = 0, 
    RTE_ETH_FDIR_REPORT_ID,            
    RTE_ETH_FDIR_REPORT_ID_FLEX_4,     
    RTE_ETH_FDIR_REPORT_FLEX_8,        
};

struct rte_eth_fdir_action {
    uint16_t rx_queue;        
    enum rte_eth_fdir_behavior behavior;     
    enum rte_eth_fdir_status report_status;  
    uint8_t flex_off;
};

struct rte_eth_fdir_filter {
    uint32_t soft_id;
    struct rte_eth_fdir_input input;    
    struct rte_eth_fdir_action action;  
};

struct rte_eth_fdir_masks {
    uint16_t vlan_tci_mask;   
    struct rte_eth_ipv4_flow   ipv4_mask;
    struct rte_eth_ipv6_flow   ipv6_mask;
    uint16_t src_port_mask;
    uint16_t dst_port_mask;
    uint8_t mac_addr_byte_mask;
    uint32_t tunnel_id_mask;
    uint8_t tunnel_type_mask; 
};

enum rte_eth_payload_type {
    RTE_ETH_PAYLOAD_UNKNOWN = 0,
    RTE_ETH_RAW_PAYLOAD,
    RTE_ETH_L2_PAYLOAD,
    RTE_ETH_L3_PAYLOAD,
    RTE_ETH_L4_PAYLOAD,
    RTE_ETH_PAYLOAD_MAX = 8,
};

struct rte_eth_flex_payload_cfg {
    enum rte_eth_payload_type type;  
    uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];
};

struct rte_eth_fdir_flex_mask {
    uint16_t flow_type;
    uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN];
};

struct rte_eth_fdir_flex_conf {
    uint16_t nb_payloads;  
    uint16_t nb_flexmasks; 
    struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
    struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
};

enum rte_fdir_mode {
    RTE_FDIR_MODE_NONE      = 0, 
    RTE_FDIR_MODE_SIGNATURE,     
    RTE_FDIR_MODE_PERFECT,       
    RTE_FDIR_MODE_PERFECT_MAC_VLAN, 
    RTE_FDIR_MODE_PERFECT_TUNNEL,   
};

#define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
#define RTE_FLOW_MASK_ARRAY_SIZE \
    (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)

struct rte_eth_fdir_info {
    enum rte_fdir_mode mode; 
    struct rte_eth_fdir_masks mask;
    struct rte_eth_fdir_flex_conf flex_conf;
    uint32_t guarant_spc; 
    uint32_t best_spc; 
    uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
    uint32_t max_flexpayload; 
    uint32_t flex_payload_unit;
    uint32_t max_flex_payload_segment_num;
    uint16_t flex_payload_limit;
    uint32_t flex_bitmask_unit;
    uint32_t max_flex_bitmask_num;
};

struct rte_eth_fdir_stats {
    uint32_t collision;    
    uint32_t free;         
    uint32_t maxhash;
    uint32_t maxlen;       
    uint64_t add;          
    uint64_t remove;       
    uint64_t f_add;        
    uint64_t f_remove;     
    uint32_t guarant_cnt;  
    uint32_t best_cnt;     
};

enum rte_eth_fdir_filter_info_type {
    RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
    RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT,
    RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
};

struct rte_eth_fdir_filter_info {
    enum rte_eth_fdir_filter_info_type info_type; 
    union {
        struct rte_eth_input_set_conf input_set_conf;
    } info;
};

enum rte_eth_hash_filter_info_type {
    RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
    RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT,
    RTE_ETH_HASH_FILTER_GLOBAL_CONFIG,
    RTE_ETH_HASH_FILTER_INPUT_SET_SELECT,
    RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
};

#define RTE_SYM_HASH_MASK_ARRAY_SIZE \
    (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)

struct rte_eth_hash_global_conf {
    enum rte_eth_hash_function hash_func; 
    uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
    uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
};

struct rte_eth_hash_filter_info {
    enum rte_eth_hash_filter_info_type info_type; 
    union {
        uint8_t enable;
        struct rte_eth_hash_global_conf global_conf;
        struct rte_eth_input_set_conf input_set_conf;
    } info;
};

struct rte_eth_l2_tunnel_conf {
    enum rte_eth_tunnel_type l2_tunnel_type;
    uint16_t ether_type; /* ether type in l2 header */
    uint32_t tunnel_id; /* port tag id for e-tag */
    uint16_t vf_id; /* VF id for tag insertion */
    uint32_t pool; /* destination pool for tag based forwarding */
};

#ifdef __cplusplus
}
#endif

#endif /* _RTE_ETH_CTRL_H_ */